The present invention relates to the field of integrated circuit fabrication. Specifically, the present invention relates to a structure and method for fabricating bipolar transistors.
One of the properties which inhibits the high frequency and high speed digital operation of bipolar transistors is the capacitive coupling between the base and the collector and emitter of the bipolar transistor. The capacitive coupling occurs across the depletion regions of the respective junctions. This phenomenon is well known and is explained in Sze, PHYSICS OF SEMICONDUCTOR DEVICES, pp. 79-81(1981). Using simple a parallel plate capacitor model, the equation for the capacitance of a junction is
C=K oA/d where,
C is the capacitance of the junction,
k is the dielectric constant of the material between the xe2x80x9cplatesxe2x80x9d of the capacitor,
eo is the permitivity of free space,
A is the area of the xe2x80x9cplatesxe2x80x9d, and
d is the width of the junction depletion region.
Thus the capacitance of a junction is directly proportional to the area of the junction and is inversely proportional to the width of the junction depletion region. Thus, there are three ways of decreasing the capacitance of a junction: decreasing the dielectric constant of the junction material or a portion of the junction, decreasing the area of the junction and increasing the thickness of the junction. Because the active junction must consist of semiconductor material, it is usually impractical to change the dielectric constant of the active junction. Therefore, in order to reduce the capacitance of a junction, the active junction area must be decreased, the effective junction thickness must be increased and/or the dielectric constant of the parasitic junction regions must be decreased.
FIG. 1 is a side view of a prior art horizontal bipolar transistor. An N-type epitaxial layer is formed on substrate 1 and isolation oxide regions 2 are formed in this epitaxial layer. Base region 5, collector region 3 and emitter region 4 are formed in the epitaxial layer. Parasitic capacitances occur between the base and both the collector and the emitter. It is an object of the present invention to minimize these capacitances in a horizontal bipolar transistor.
In one embodiment of a horizontal bipolar transistor constructed in accordance with the teachings of this invention, oxygen is implanted into the horizontal bipolar transistor to provide a silicon dioxide layer between the base region and both the collector and the emitter of the horizontal bipolar transistor. This silicon dioxide layer reduces the actual interface area of the base to collector and base to emitter junctions, thereby decreasing the capacitance transistor. In addition, the thickness and dielectric constant of the silicon dioxide layer is such that the capacitance across the silicon dioxide layer, and thus between the base and the emitter of collector, is minimal relative to the base to emitter or collector capacitance provided by the base to emitter or collector junction itself because the dielectric constant of silicon dioxide is approximately 3.9 which is much less than the dielectric constant of crystalline silicon which is approximately 11.7.
In an alternative embodiment, nitrogen ions are implanted to form silicon nitride regions rather than silicon dioxide regions.
In yet another alternative embodiment, oxygen and nitrogen ions are implanted to form both silicon nitride and silicon dioxide regions rather than either species alone.